From: jge@cs.unc.edu (John Eyles)
Subject: Re: Highest Performance VR System
Date: 12 Aug 91 19:41:35 GMT
Organization: University of North Carolina, Chapel Hill



In article <1991Aug10.003933.5870@milton.u.washington.edu> psantangeli@alias.com (Peter Santangeli) writes:
>
>
>In article <1991Aug7.001635.11441@milton.u.washington.edu>, mklapman@adsl (Matth
>ew Klapman) writes:
>
>> ... Each pixel has its own processor (massively parallel!!!), and
>> the processor would decide whether it should be on or off.  Each pixel
>> receives the same set of parameters at the same time as all the rest.
>> 
>> Anyway, I'm not an expert on it, but was very impressed with their research
>> team.  I hear that version 6 will have its design completed this month.
>
>Having said that, perhaps we could have someone from UNC comment on the
>*actual* capabilities of the Pixel Planes. As far as I know (having taken
>Henry Fuchs's Sigraph course in 89), there is NOT one processor per pixel,
>but one custom processor for every 128x128 pixel block. On top of that run a
>set (<100) of i860 processors.

I'm one of the primary architects (and designers, and builders, and
assemblers, and debuggers) of the Pixel-Planes systems and their planned
successors. I'll try to clarify things a little.

Pixel-Planes 4, the first full-scale prototype (shown at Siggraph '86)
did indeed have a processor (bit-serial) per pixel. However, the real
power of these processors comes from the distributed linear expression
evaluator which simultaneously supplies each pixel processor with it's
specific local value of the expression Ax + By + C. In this system,
performance was completely independent of triangle size (as a previous
poster commented).  But because it was a massive SIMD array, processor
utilization was very poor (i.e.: 512 x 512 = 1/4 million processors
working on the "typical" 100 pixel polygon).

So we went to Pixel-Planes 5. In this machine, there are multiple
"Renderer" units. Each Renderer is sort of like a mini-Pixel-Planes 4;
it is a 128 x 128 pixel SIMD array of processors with a distributed
quadratic expression evaluator. The multiple Renderers operate on
separate sets of polygons and can be dynamically reassigned to
different regions of the screen.  In this machine (the one shown at
Siggraph 91 Tomorrow's Realities) performance is NOT totally independent
of screen size, because bigger polygons are more likely to fall into
more than one 128 x 128 region; however, performance is certainly much
less dependent on polygon size than with most commercial architectures.
(See Fuchs and Poulton et al. in Siggraph '89 for details).

Pixel-Planes 5 is *actually* capable of drawing more than two million
triangles per second. This figure means polygons that are presented on
the screen to a user in a real application; it does not mean the number
of polygons traversed by the geometry pipeline and it does not include
back-facing polygons. The polygons are Phong-shaded with 24-bit color
and Z-buffered. Most of the demos we showed in Las Vegas didn't show
the max triangle rendering number, either because the models were too
simple or because the models included textured polygons and they eat
into the performance (as you might expect).  We did occasionally show a
demo on a terrain data set which showed the 2 million number (and
indulged ourselves by passing out little buttons to that effect).

As far as future plans, THERE WILL NOT BE A PIXEL-PLANES 6.  We
certainly plan to continue working on new architectures, and we do have
tentative plans for a new machine. It will incorporate many of the
Pixel-Planes ideas, i.e.: processor enhanced memory chips with
distributed polynomial expression evaluators.  However, the system
level approach to parallelizing the rendering calculations will be
radically different from what is done in Pixel-Planes 5.

Stay tuned.